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TECHNICAL DATA
IW4040B
12-Stage Binary Ripple Counter
High-Voltage Silicon-Gate CMOS
The IW4040B is ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. * * * Operating Voltage Range: 3.0 to 18 V Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25C Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply
N SUFFIX PLASTIC DIP
16 1 16 1
ORDERING INFORMATION IW4040BN IW4040BD IZ4040B Plastic DIP SOIC chip
TA = -55 to 125 C for all packages
LOGIC DIAGRAM
9 Q1 7 Q2 6 Q3 CLOCK 10 5 3 2 4 13 12 14 15 1 Q12 11 RESET Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11
Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V CC Q11 Q10 Q8 Q9 RESET CLOCK Q1
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Clock Reset L L X H= high level L = low level X=don't care H Output Output state No change Advance to next state All Outputs are low
PIN 16 =VCC PIN 8 = GND
INTEGRAL
1
IW4040B
MAXIMUM RATINGS *
Symbol VCC VIN VOUT IIN PD Ptot Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 10 500* 1 100 -65 to +150 260
Unit V V V mA mW mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 For TA=-55 to 100C (package plastic DIP), for TA=-55 to 65C (package SOIC) +Derating - Plastic DIP: - 12 mW/C from 100N to 125C SOIC Package: : - 7 mW/C from 65N to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
INTEGRAL
2
IW4040B
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Test Conditions V VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V VIN= GND or VCC 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 -55C 3.5 7.0 11.0 1.5 3.0 4.0 4.95 9.95 14.95 0.05 0.05 0.05 0.1 5 10 20 100 0.64 1.6 4.2 -2.0 -0.64 -1.6 -4.2 25C 3.5 7.0 11.0 1.5 3.0 4.0 4.95 9.95 14.95 0.05 0.05 0.05 0.1 5 10 20 100 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4 Guaranteed Limit 125 C 3.5 7.0 11.0 1.5 3.0 4.0 4.95 9.95 14.95 0.05 0.05 0.05 1.0 150 300 600 3000 0.36 0.9 2.4 mA -1.15 -0.36 -0.9 -2.4 Unit V
VIL
V
VOH
V
VOL
VIN= GND or VCC
V
IIN ICC
VIN= GND or VCC VIN= GND or VCC
A A
IOL
VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V VIN= GND or VCC UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V
mA
IOH
Minimum Output High (Source) Current
INTEGRAL
3
IW4040B
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, RL=200 k, t r=t f=20 ns)
Symbol fmax Parameter Maximum Clock Frequency (Figure 1) VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Guaranteed Limit -55C 3.5 8 12 360 160 130 330 80 60 280 120 100 200 100 80 25C 3.5 8 12 360 160 130 330 80 60 280 120 100 200 100 80 7.5 125C 1.75 4.0 6.0 720 320 260 660 160 120 560 240 200 400 200 160 MHz Unit
tPLH, t PHL
Maximum Propagation Delay, Clock to Q1 (Figure 1)
ns
tPLH, t PHL
Maximum Propagation Delay, Qn to Qn+1 (Figure 2)
ns
tPHL
Maximum Propagation Delay, Reset to Any Q (Figure 3) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance
ns
tTLH, t THL
ns
CIN
pF
TIMING REQUIREMENTS (CL=50 pF, RL=200 k, t r=t f=20 ns)
Symbol tw Parameter Minimum Pulse Width, Clock (Figure 1) VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Guaranteed Limit -55C 140 60 40 200 80 60 350 150 100 25C 140 60 40 200 80 60 350 150 100 Unlimited 125C 280 120 80 400 160 120 700 300 200 ns Unit
tw
Minimum Pulse Width, Reset (Figure 3)
ns
trem
Minimum Removal Time, Reset(Figure 3)
ns
tr, tf
Maximum Input Rise and Fall Times, Clock (Figure 1)
ns
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
INTEGRAL
4
IW4040B
50%
VCC GND
CLOCK tw RESET
50%
trem VCC GND
t PHL
50%
VCC GND
ANY Q
Figure 3. Switching Waveforms
TIMING DIAGRAM
0 Clock Reset Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 1 2 4 8 16 32 64 128 256 512 1024 2048 4096
EXPANDED LOGIC DIAGRAM
CL1 FF1
Q1
CL2 FF2
Q2
CL3
Q11
CL7 FFI2
Q12
CLOCK RESET
CL1 R
Q1 Q1
CL2 R
Q2
CL3 FF3-FF11
Q11
CL7 R
Q12
Q1
Q2
Q3
Q11
Q12
INTEGRAL
5
IW4040B
INTEGRAL
6
IW4040B
CHIP PAD DIAGRAM
Chip marking 4040 11 14 15 2.02 + 0.03 16 09 01 08 13 12 10
02
03
04
05
06
07
Y
(0,0)
X
2.28 + 0.03
Location of marking (mm): left lower corner x=0.199, y=1.792. Chip thickness: 0.46 0.02 (0.35 0.02 ) mm. PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 Symbol Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND Q1 INPUT RES Q9 Q8 Q10 Q11 VCC Location (left lower corner), mm X Y 0.1525 0.9025 0.1525 0.2315 0.4515 0.1525 0.8115 0.1525 1.1715 0.1525 1.5315 0.1525 2.0270 0.3365 2.0270 0.7995 2.0270 1.0135 2.0270 1.4760 1.8470 1.7675 1.2430 1.7675 0.9965 1.7675 0.4445 1.7675 0.1525 1.5980 0.1525 1.2140 Pad size, mm 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100
Note: Pad location is given as per passivation layer
INTEGRAL
7

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